1. Field of the Invention
The present invention relates generally to strained silicon layer structures employed within semiconductor products. More particularly, the present invention relates to reduced dislocation defect density strained silicon layer structures employed within semiconductor products.
2. Description of the Related Art
As semiconductor product performance requirements have increased, so also have evolved novel semiconductor materials and structures which provide enhanced semiconductor product performance. Included among such novel materials and structures are strained silicon materials and structures which may be employed as substrates when forming semiconductor devices. Strained silicon materials and structures are desirable as semiconductor substrates insofar as strained silicon materials provide for enhanced carrier mobility and thus enhanced performance of semiconductor devices.
While strained silicon materials and structures are thus desirable in the art of semiconductor fabrication, they are nonetheless not entirely without problems. In that regard, it is often difficult in the art of semiconductor fabrication to provide strained silicon layer structures with attenuated strain induced defects, such as strain induced dislocation defects.
It is thus desirable in the semiconductor fabrication art to provide strained silicon layer structures with attenuated strain induced defects.
It is towards the foregoing object that the present invention is directed.
Various strained silicon layer structures having desirable properties, and methods for fabrication thereof, have been disclosed in the semiconductor fabrication art.
Included among the strained silicon layer structures and methods, but not limiting among the strained silicon layer structures and methods, are strained silicon layer structures and methods disclosed within: (1) Ismail et al., in U.S. Pat. No. 5,534,713 (a strained silicon layer structure suitable for fabrication of complementary metal oxide semiconductor (CMOS) field effect transistor (FET) devices); (2) Ek et al., in U.S. Pat. No. 5,759,898 (a strained silicon layer structure with attenuated dislocation defects); (3) Liaw et al., in U.S. Pat. No. 5,891,769 (a thermal annealing method for forming a strained silicon layer structure); and (4) Sugiyama et al., in U.S. Pat. No. 6,326,667 (an oxygen implant method for forming a strained silicon layer structure).
The teachings of each of the foregoing references are incorporated herein fully by reference.
Desirable in the semiconductor fabrication art are additional strained silicon layer structures with attenuated strain induced defects.
It is towards the foregoing object that the present invention is directed.